Internship Generic Correctness Of Iterative Cirtical Software Architecture Exploration-Saclay H/F CEA
- Saclay - 91
- Stage
- 6 mois
- Bac +5
- Industrie high-tech • Telecom
Les missions du poste
As an intern at the CEA, you will have the opportunity to work within a world-renowned research environment. Our teams consist of passionate and dedicated experts, providing an ideal setting for learning and collaboration. You will have access to state-of-the-art equipment and top-tier research resources to carry out your assignments. The work conducted may potentially lead to a scientific publication.
Context :
The QuaRTOS-DSE tool explores the design space of a critical application by applying, in sequence, strategies that group its functions into tasks, each producing an architecture Mi+1 from Mi. Recent work (VECoS 2026) defines preservation properties that every correct reclustering must satisfy, checked with TLA+ and the TLC model checker: conservation of the configuration, correspondence of the executions per function and per task, and preservation of the communication. It was extended to partitioned multicore deployments and to the coherence of the data each function reads.
These properties are necessary but not sufficient: a reclustering can satisfy all of them without preserving the behavior of the system. Each architecture is compared only with the one it came from, with no guarantee that the verdicts compose along an exploration. Finally, the multicore model assumes that each task stays on its core, and ignores interference from shared hardware resources.
The internship aims to remove these three limitations.
What do we expect from you?
Study the existing work: the formal model of QuaRTOS-DSE, the preservation properties and their TLA+ models,
Complete the necessary equivalence properties between two architectures with new properties, to reach a sufficient condition,
Propose a solution or a proof for the coverage of the properties with respect to the iterative exploration: establish under which conditions Mi Mi+1 ... Mk implies Mi Mk,
Extend the multicore model to account for task migration between cores and interference from shared hardware resources,
Evaluate the proposals on existing use cases, including an industrial protection relay, and measure their verification cost.
During this internship, the student will gain practical experience with safety-critical systems and formal verification techniques, in particular model checking.
--
Methods / Means: TLA+/TLC, Python, EMF/xtext
Level required: Master's degree, Bac +5 - Master of Science
Duration: 6 months
Skills: Understanding of critical embedded and real-time software; knowledge of formal methods (temporal logic, model checking) is expected. Fluent English, teamwork, curiosity
~1400€ monthly "salary", depending on whether the intern has a scholarship or not.
In line with CEA's commitment to integrating people with disabilities, this job is open to all.
Location: Site Saclay, France, Ile-de-France, Essonne (91), Palaiseau
Start date: to be defined
Contact: ****@****.**, ****@****.**
#Cea-List
Le profil recherché
Master's degree, Bac +5 - Master of Science
Understanding of critical embedded and real-time software; knowledge of formal methods (temporal logic, model checking) is expected. Fluent English, teamwork, curiosity
Les avantages
- Télétravail jusqu’à 3 jours par semaine
- 52 jours de congés/RTT
- Possibilité d’aménagement du temps de travail
- Formation personnalisée
- Restauration d’entreprise
- Offre de transport interne et prise en charge Navigo and co,
- Mutuelle d’entreprise avantageuse
- CE (aides vacances, loisirs, frais de garde, scolarité des enfants etc
Les étapes de recrutement
Les étapes de recrutement peuvent varier selon l'offre à laquelle vous postulez.
-
Dépôt de CV via notre site carrière
-
Préqualification téléphonique
-
Entretiens et évaluation avec manager et RH
-
Négociation salariale et contrat de travail
-
Embauche et intégration
-
CEA en images
Publiée le 20/10/2026 - Réf : 2026-42194
