Phd Position F - M Scalable Reliability Assessment Under Natural Faults And Adversarial Perturbations H/F

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PhD Position F/M Scalable Reliability Assessment Under Natural Faults and Adversarial Perturbations
Le descriptif de l'offre ci-dessous est en Anglais
Type de contrat : CDD

Niveau de diplôme exigé : Bac +5 ou équivalent

Fonction : Doctorant

A propos du centre ou de la direction fonctionnelle

The Inria Centre at Rennes University is one of Inria's eight centres and has more than thirty research teams. The Inria Centre is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

Contexte et atouts du poste

Context

Modern embedded systems deployed in safety-critical domains-automotive, aerospace, robotics, drones, and industrial control-must simultaneously satisfy functional safety, reliability, and security constraints. As hardware architectures become more complex, assessing their reliability under realistic fault conditions becomes increasingly challenging. Traditional fault models and evaluation methods do not scale to modern architectures, and they often overlook interactions with reliability and security. Thus, there is a pressing need for scalable and accurate reliability assessment methodologies that cover both environmental/natural faults and intentional attacks (i.e. adversarial perturbations), given their similar underlying physical effects.

A hardware perturbation, by means of an intentional fault injection, aims at inducing logical changes either at the hardware or software levels, such that the target system reaches unexpected states or follows unexpected execution paths. Fault injections thus allow an attacker to move the target processor out of its expected functioning bounds. Reaching such unexpected states is then leveraged
in attacks for leaking secrets, escalating privileges, etc. From a reliability perspective, hardware perturbations - typically caused by environmental conditions (e.g., radiation) are analyzed in terms of their probability of leading to system failures rather than their ability to reach specific adversarial states. The objective is not to steer the system toward a particular malfunction, but to quantify the likelihood that faults propagate to observable errors violating safety requirements, such as incorrect outputs, missed deadlines, loss of control, or system crashes. Background. Recently, formal methods have been applied to analyze the robustness of systems against fault injection attacks [TAC+23]. This methodology offers a rigorous approach to formally analyze the impact of faults at the processor microarchitecture level and their consequences on software execution. By construction, formal methods guarantee exhaustive coverage of all possible states of the system, thereby meeting the completeness requirements of security analyses. Nevertheless, this approach suffers from scalability limitations due to the complexity of processor microarchitecture models, the depth of software execution required in the formal analysis, and the state explosion induced by fault injections. Initial efforts to mitigate this state-space explosion have been successfully undertaken by exploiting redundancy-based hardware countermeasures in the formulation of properties to be proven [THN+24].

On the other hand, fault injection through simulation is typically used for vulnerability analysis. However, exhaustively applying fault injection is not feasible; thus, methods are needed to reduce the
time required for vulnerability analysis while maintaining high accuracy. These methods include i) fault injection frameworks based on Statistical Fault Injection (SFI) [GKH+25], which mathematically estimates the number of faults to be injected in order to obtain statistically confident results, ii) combining different system abstraction layers during simulation [TTdSK26a], where the majority of the application execution is done at higher abstraction layer and only the fault injection occurs at low abstraction layer, such as RTL, and iii) parallel fault injection, where several fault are injected concurrently to reduce the number of required fault injections [TTdSK26b].

PhD Topic

The goal of the PhD is to provide a unified framework for analyzing the impact of fault injection on microarchitectural security and reliability, with a focus on RISC-V processors and domain-specific accelerators. To achieve that, it is expected to create realistic models for the environmental faults and attacks under study, taking into account as much as possible the microarchitecture. Then, methodologies needed to evaluate system security and reliability will be proposed, along with post-analysis techniques to identify the most vulnerable components. In particular, a hybrid approach will be investigated, combining the strengths of formal methods and multilevel fault-injection simulation to address scalability challenges in complex systems when verifying these non-functional properties. An implementation of this methodology, possibly using the Circuit Intermediate Representation (IR) Compilers and Tools (CIRCT) framework [CIR], will be developed and used to guide the exploration of the architectural state space with respect to reliability and security metrics over a set of hardware blocks (such as Comet processor [SR22] for instance). Post-analysis techniques will also support the development of potential countermeasures.

References
[CIR] CIRCT / circuit IR compilers and tools. Available: https://circt.llvm.org/.

[GKH+25] Wilfread Guillem´e, Angeliki Kritikakou, Youri Helen, C´edric Killian, and Daniel Chillet. Fault tolerance in quantized and pruned convolutional neural networks. In 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), pages 1-7, 2025.

[SR22] Olivier Sentieys Simon Rokicki, Joseph Paturel. Comet: a RISC-V Core Synthesizedfrom C++ Specifications. In Spring RISC-V Week, 2022.

[TAC+23] Simon Tollec, Mihail Asavoae, Damien Courouss´e, Karine Heydemann, and Mathieu Jan. ArchiFI: Formal Modeling and Verification Strategies for Mmicroarchitetural Fault Injections. In FMCAD. 23-Formal Methods in computer-Aided Design 2023, pages 101-109. TU Wien Academic Press, 2023

[THN+24] Simon Tollec, Vedad Hadzic, Pascal Nasahl, Mihail Asavoae, Roderick Bloem, Damien Courouss´e, Karine Heydemann, Mathieu Jan, and Stefan Mangard. Fault-resistant partitioning of secure cpus for system co-verification against faults. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024(4):179-204, 2024.

[TTdSK26a] Rafael Billig Tonetto, Marcello Traiola, Fernando Fernandes dos Santos, and Angeliki Kritikakou. Enfor-sa: End-to-end cross-layer transient fault injector for efficient and accurate dnn reliability assessment on systolic arrays. In 2026 IEEE VLSI Test Symposium, 2026.

[TTdSK26b] Rafael Billig Tonetto, Marcello Traiola, Fernando Fernandes dos Santos, and Angeliki
Kritikakou. Scalable reliability assessment of dnns through simultaneous fault injection.
In 2026 IEEE/ACM Design Automatoon Conference (DAC), 2026.

Compétences

Candidate Profile

The candidate should be familiar with the following:
- Strong background in probability, statistics, and discrete mathematics for modeling faults and analyzing system behavior.
- Knowledge of computer architecture and digital hardware design, including HDL languages such as Verilog or VHDL.
- Experience with hardware simulation, verification, or formal methods.
- Interest or experience in hardware security, fault injection, or reliability analysis (RISC-V knowledge is a plus).

Institute.

The PhD will take place at Inria in Rennes, France, in the TARAN Inria team. This team is part of the IRISA laboratory. The PhD will be co-advised by Angeliki Kritikakou (Inria), Fernando Fernades dos Santos (Inria), Marcello Traiola (Inria), Mathieu Jan (CEA list) and Damien Courouss´e(CEA list).

Practical aspects.

This PhD will last 3 years. Additional teaching activities are not mandatory, but possible. Such complementary activities give rise to an additional salary. The PhD can be precededby a Master's internship on the same topic.

Avantages

- Subsidized meals
- Partial reimbursement of public transport costs
- Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
- Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
- Professional equipment available (videoconferencing, loan of computer equipment, etc.)
- Social, cultural and sports events and activities
- Access to vocational training

Rémunération

monthly gross salary 2300 euros