Cocorisco R&D Engineer In Hardware Platforms For Research And Education H/F INRIA

Cocorisco: R&D Engineer in Hardware Platforms for Research and Education
Le descriptif de l'offre ci-dessous est en Anglais
Type de contrat : CDD

Contrat renouvelable : Oui

Niveau de diplôme exigé : Bac +5 ou équivalent

Autre diplôme apprécié : PhD in Computer Engineering

Fonction : Ingénieur scientifique contractuel

A propos du centre ou de la direction fonctionnelle

The Centre Inria de l'Université de Grenoble groups together almost 600 people in 26 research teams and 9 research support departments.

Staff is present on three campuses in Grenoble, in close collaboration with other research and higher education institutions (Université Grenoble Alpes, CNRS, CEA, INRAE, ...), but also with key economic players in the area.

The Centre Inria de l'Université Grenoble Alpes is active in the fields of high-performance computing, verification and embedded systems, modeling of the environment at multiple levels, and data science and artificial intelligence. The center is a top-level scientific institute with an extensive network of international collaborations in Europe and the rest of the world.

Contexte et atouts du poste

The Centre Inria de l'Université de Grenoble groups together almost 600 people in 22 research teams and 7 research support departments.

Staff is present on three campuses in Grenoble, in close collaboration with other research and higher education institutions (Université Grenoble Alpes, CNRS, CEA, INRAE, ...), but also with key economic players in the area.

The Centre Inria de l'Université Grenoble Alpe is active in the fields of high-performance computing, verification and embedded systems, modeling of the environment at multiple levels, and data science and artificial intelligence. The center is a top-level scientific institute with an extensive network of international collaborations in Europe and the rest of the world.

You will takepart of the Défi Inria Cocorisco (https://project.inria.fr/cocorisco/) that regroups multiple Inria teams (MADMax, Taran, Benagil, Corse, SUSHI and PACAP) and CEA List (DSCIN) to work on several aspects of modern general purpose hardware systems (performance, energy-efficiency, reliability, security) using the RISC-V ISA as common denominator. In this context, we would like to devise and maintain an experimental platform in which contributions could be validated. This platform is expected to be open-source and usable by anyone.

You will join theMADMax joint Inria-TIMA research team. And your office will be located in the TIMA laboratory in Grenoble.

Mission confiée

We are looking for candidates to take ownership of the development of an RTL-level experimental CPU platform to serve as a vessel for validating research ideas.

As several platforms already exist, the goal is not to start from scratch, but to identify a reasonable baseline to build on, and to provide "off the shelf" releases of the platform to the project members and to the wider national scientific community.

Principales activités

First, perform a survey of existing platforms to determine, in conjunction with the Défi members, which existing project to build on. There are several key points that need to be taken into account, such as the language in which the platform is developped (e.g., Chisel vs. Verilog/VHDL), the current maturity of the platform, the current complexity of the platform (e.g., embedded vs. high performance). Ideally, this platform should be useable both in a research context and in a teaching context (e.g., M2 level).

Second, the actual creation of the platform by forking the chosen baseline. Depending on the maturity of the baseline platform, this may involve adding documentation, code examples, strengthen continuous integration. Depending on the target of the platform (FPGA or ASIC), you may also go through the motions of implanting the design on FPGA and setting up a physical testbench. You will also be tasked with packaging an "off the shelf" release using e.g., Docker.

Third, as the platform matures, you will be tasked with publicizing it, e.g., by contacting potential stakeholders in the national community that go beyond the Défi, and by organizing tutorials at national events (e.g., Colloque du GDR SOC², Conférence COMPAS).

Fourth, over the duration of the contract, you will provide support to Défi members as they move forward with the validation of scientific contributions in the platform.

Compétences

Master's degree in Computer Science (PhD is appreciated)

Expected technical skills are:
- Hands-on experience with RTL design (Verilog, VHDL, Chisel)
- Hands-on experience with high-level programming (e.g., Python, Java, C/C++). Scala is a plus as Chisel is embedded in Scala.
- Hands-on experience with scripting languages (e.g., Python, Bash)
- Hands-on experience with version management tools (git)
- Basic knowledge of continuous integration flows and infrastructure (gitlab)
- As support may have to be provided for both english and french speakers, a B2 level in french and english is expected.

Avantages

- Subsidized meals
- Partial reimbursement of public transport costs
- Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
- Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
- Professional equipment available (videoconferencing, loan of computer equipment, etc.)
- Social, cultural and sports events and activities
- Access to vocational training
- Social security coverage under conditions

Rémunération

From 2,692 € (depending on experience and qualifications).